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https://github.com/mrsamsonn/vlsi-project
VLSI Project for CMPE 480______ Authors: John San Juan, Cody Hum, Vincent Verdan, Jose Zaragosa
https://github.com/mrsamsonn/vlsi-project
gates logic logisim magic vlsi-circuits vlsi-design
Last synced: 2 days ago
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VLSI Project for CMPE 480______ Authors: John San Juan, Cody Hum, Vincent Verdan, Jose Zaragosa
- Host: GitHub
- URL: https://github.com/mrsamsonn/vlsi-project
- Owner: mrsamsonn
- Created: 2024-03-19T06:53:32.000Z (9 months ago)
- Default Branch: main
- Last Pushed: 2024-05-07T16:35:11.000Z (8 months ago)
- Last Synced: 2024-12-10T19:46:56.264Z (12 days ago)
- Topics: gates, logic, logisim, magic, vlsi-circuits, vlsi-design
- Language: Batchfile
- Homepage:
- Size: 5.86 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
## vlsi-project
Project: Register File + ALU
 
**Milestone Checklist**
- [x] Preliminary project cell layouts: defines full schematic hierarchy and functionality.
- [x] updated version of your milestone #2 writeup with any changes based on comments made. [ updated MS#2 submission with errors fixed (Canvas)]
- [x] conclusion is missing.
- [x] drop multiplication for ALU
- [x] schematic is not working
- [x] demonstrate loading of values to the reg file and operating on them
- [x] Please only include one test harness. It should consist of input pins, output ins, and a single part.
- [x] Please turn off the three-state inputs on your input pins
- [x] DFFs have serious design flaws. Please fix Logisim simulation is not working.
- [x] Many of the layouts submitted have design errors in them.
- [x] Please include .cmd files to demonstrate that the layouts simulate proerly
- [x] complete Logisim/LogicWorks schematic (Canvas command)
- [x] .cmd test files for IRSIM (turnin command)
- [x] partially complete set of Magic layouts for standard cells (these should only be submitted if DRC correct) (turnin command)
---
**Magic Hierarchy Development [Layer0 - Layer4]**
-- ** *Layer0: transistor-level* **
- [x] magic: OR2 gate
- [x] magic: NOR2 gate
- [x] magic: INV
- [x] magic: OR3 gate
- [x] magic: OR4 gate
- [x] magic: NAND2 gate
- [x] magic: XOR2 gate
- [x] magic: AND2 gate
- [x] magic: AND3 gate
-- ** *Layer1: gate-level* **
- [x] magic: 1-bit MUX3
- [x] magic: 1-bit MUX2
- [x] magic: 1-bit MUX8
- [x] magic: 1-bit 3-to-8 Decoder
- [x] magic: 1-bit D Flip Flop
- [x] magic: 1-bit full-Adder
- [x] magic: 1-bit full-Subtractor
- [x] magic: 1-bit half-Adder
- [x] magic: 1-bit half-Subtractor
- [x] magic: 4-bit AND2
- [x] magic: 4-bit OR2
- [x] magic: 4-bit NAND2
- [x] magic: 4-bit NOR2
-- ** *Layer2: parts-level* **
- [x] magic: 4-bit MUX3
- [x] magic: 4-bit MUX8
- [x] magic: 4-bit Register
- [x] magic: 1-bit DFF with Enabler [merge MUX2 + DFF]
- [x] magic: 4-bit Adder
- [x] magic: 4-bit Subtractor
-- ** *Layer3: block-level* **
- [x] magic: 4-bit Register File
- [x] magic: 4-bit ALU
-- ** *Layer4: top-level [single block]* **
- [x] magic: 4-bit single-block [merge MUX3 + Register File + ALU]
---
**Progress**
- [x] Logisim functional (unless bugs/issues encountered)
- [x] magic gate layouts
- [x] make a single block as top level
- [x] make sure all magic simulates properly (will help us in the long run before we build the parts)
- [x] build MUX3 in magic?
- [x] build Register File in magic?
- [x] build ALU in magic?
**Issues**
- [x] Fix DFF incorrect output
- [x] Fix Oscillation Apparent
**Workload**
- [x] Remove Multiplier
- [x] 8 bits to 4 bits
- [ ] Remove MUX3?
- [ ] cut down number of registers? (8 registers currently)
Abstract:
This project shows three crucial blocks: MUX3, Register File, and Arithmetic Logic Unit (ALU). The MUX3 selects data for storage in the Register File, which features 8 registers and dynamic address selection. The ALU performs arithmetic operations based on user selection, producing 4-bit results. Also, the ALU's output loops back to the MUX3, forming a crucial feedback loop for iterative calculations. Understanding these blocks is essential for understanding computing systems.
Parts: MUX3, Reg File, ALU
**Top level**
# MUX3 Hierarchy
---
4 bit MUX3
1 bit MUX
# Register File Hierarchy
---
Register File
MUX8 (to cover 8 registers)
4 bit Register
D Flip Flop + MUX2[as enabler]
D Flip Flop
# ALU Hierarchy
---
ALU (Need one more logic to replace multiplier)
