https://github.com/mrvideo/rl23
https://github.com/mrvideo/rl23
Last synced: 3 months ago
JSON representation
- Host: GitHub
- URL: https://github.com/mrvideo/rl23
- Owner: MrVideo
- Created: 2023-05-30T19:38:43.000Z (about 2 years ago)
- Default Branch: master
- Last Pushed: 2024-05-17T21:45:01.000Z (about 1 year ago)
- Last Synced: 2025-03-11T00:48:31.915Z (3 months ago)
- Language: VHDL
- Size: 1.04 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Progetto di Reti Logiche
This repository contains the project made for the "Reti Logiche" course at Politecnico di Milano for the academic year 2022/2023.
This project was carried out by my colleague, [Riccardo Manfredonia](https://github.com/manfroso), and myself.
The aim of the project was to create a small memory controller in VHDL to access some data and output it through four ports. The software used for this project was [Xilinx Vivado](https://www.xilinx.com/products/design-tools/vivado.html).
You can read more about it in the [report](REPORT.md) (written in Italian). Since there are some formatting issues with the MarkDown file, I also provided a [PDF version](REPORT.pdf).