https://github.com/mshr-h/verilog_building_block

Verilog building blocks with high chance of re-use
https://github.com/mshr-h/verilog_building_block

verilog-hdl

Last synced: 8 days ago
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Verilog building blocks with high chance of re-use

• Host: GitHub
• URL: https://github.com/mshr-h/verilog_building_block
• Owner: mshr-h
• License: mit
• Created: 2015-12-20T17:09:52.000Z (almost 10 years ago)
• Default Branch: master
• Last Pushed: 2016-10-26T13:13:07.000Z (about 9 years ago)
• Last Synced: 2025-02-08T13:13:51.609Z (9 months ago)
• Topics: verilog-hdl
• Language: Verilog
• Size: 14.6 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# Verilog building blocks [![Build Status](https://travis-ci.org/mshr-h/verilog_building_block.svg)](https://travis-ci.org/mshr-h/verilog_building_block)

## Description

TBA

## Modules

- `button_debounce.v` - debouncing circuit

- `ram_sp.v` - Single port RAM

- `adder_tree.v` - Adder tree

- `shift_register.v` - Shift Register

- `synchronizer.v` - Synchronize data

- `uart_rx.v` - UART reciever(not tested on FPGA board)