Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/mssola/hdl
Playing around with Hardware Description Languages.
https://github.com/mssola/hdl
hdl systemverilog verilog
Last synced: 23 days ago
JSON representation
Playing around with Hardware Description Languages.
- Host: GitHub
- URL: https://github.com/mssola/hdl
- Owner: mssola
- License: gpl-3.0
- Created: 2024-07-10T20:12:42.000Z (5 months ago)
- Default Branch: main
- Last Pushed: 2024-07-10T20:15:23.000Z (5 months ago)
- Last Synced: 2024-10-10T06:21:54.678Z (2 months ago)
- Topics: hdl, systemverilog, verilog
- Language: C++
- Homepage:
- Size: 15.6 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- Contributing: CONTRIBUTING.md
- License: LICENSE
Awesome Lists containing this project
README
Playing around with Hardware Description Languages. Nothing too serious, just
taking a look how all of this works.## How?
All simulation is done via [Verilator](https://www.veripool.org/verilator/) and
the results are displayable with [GTKWave](https://gtkwave.sourceforge.net/).
Make sure that you have both of these dependencies installed (and beware
openSUSE's weird default installation path for Verilator!).Each design lives into its own file inside of `src`. Hence, for the `simple.vs`
design, you simply need to call:``` sh
$ make wave.simple
```This will verilate the SystemVerilog file, compile the resulting C++ code
together with its corresponding simulation from the `sim` directory, and launch
GTKWave for the resulting wave file.After you are done with all of this, simply call `make clean` and go touch some
grass.## License
Released under the [GPLv3+](http://www.gnu.org/licenses/gpl-3.0.txt), Copyright
(C) 2024-Ω Miquel Sabaté Solà.