https://github.com/msyksphinz-self/riscv-isadoc

https://github.com/msyksphinz-self/riscv-isadoc

Last synced: 4 days ago
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• Host: GitHub
• URL: https://github.com/msyksphinz-self/riscv-isadoc
• Owner: msyksphinz-self
• License: cc-by-4.0
• Created: 2019-04-14T08:00:14.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2024-04-20T05:59:08.000Z (7 months ago)
• Last Synced: 2024-08-02T19:34:25.386Z (3 months ago)
• Language: HTML
• Size: 12.4 MB
• Stars: 26
• Watchers: 2
• Forks: 11
• Open Issues: 6
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
RISC-V ISA Specification

========================

RISC-V ISA Specification web page.

## Description

This is a documentation of RISC-V ISA.

Document would be deployed at https://msyksphinz-self.github.io/riscv-isadoc/html/index.html

ISA spec is based on RISC-V User-Level ISA V2.2.

Each instruction, bit encoding is generated from RISC-V Instruction set simulator Swimmer-RISCV(https://github.com/msyksphinz/swimmer_riscv.git).

- Swimmer-RISCV instruction decode list: https://github.com/msyksphinz/swimmer_riscv/blob/master/build/riscv_arch_table.json

- Executing `gen_rst_table.rb` in https://github.com/msyksphinz/swimmer_riscv/blob/master/script/ generaets instruction bit field.

## Usage

1. Edit `./source/*.rst`

2. To generate html page, hit `make html` in root repository.

3. `./docs/html/` is referred from index.html. To deploy page, just pushing master branch.

## Author

[msyksphinz](http://github.com/msyksphinz)