https://github.com/mttcrn/logical-networks-project
Final exam of "Logical Networks" - Polimi Computer Science Engineering - A.Y. 2022-2023
https://github.com/mttcrn/logical-networks-project
fsm polimi vhdl
Last synced: 6 months ago
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Final exam of "Logical Networks" - Polimi Computer Science Engineering - A.Y. 2022-2023
- Host: GitHub
- URL: https://github.com/mttcrn/logical-networks-project
- Owner: mttcrn
- Created: 2023-03-03T16:40:57.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-10-20T15:05:54.000Z (almost 2 years ago)
- Last Synced: 2023-10-20T16:24:44.293Z (almost 2 years ago)
- Topics: fsm, polimi, vhdl
- Language: VHDL
- Homepage:
- Size: 2.24 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Logical Networks Project 2022/2023
The aim of the project is the implementation of a hardware component in VHDL which, given in input a selector and a memory address, shows the content on the selected output channel of memory, without erasing previously obtained results.
Grade obtained: 30/30.
## Problem description
The module is initialized each time the `RESET` signal is equal to 1, asynchronously with respect to the clock.
Processing begins when `START` is equal to 1, and reading of input `W` occurs on the rising edge of the clock. The input component receives a sequence consisting of two header bits, that serve to identify the target output channel, followed by the memory address bit. As soon as `START` is qeual to 0, the module send a request to the memory and selects the output channel to which the result should be directed.
When the memory produces a result, the oupout `DONE` is set to 1 and, simultaneously, the message is written to the selected output channel, while the other channels display the last transmitted value, all within a single clock cycle.
## Implementation
The implementation is achieved through a finite state machine (FSM) that represents the algorithm used, from the reading of inputs to the output writing. The entire module's operation is encapsulated within a single process, ensuring that all signals are updated predictably and synchronously.
## Authors
* [Andrea Grassi](https://github.com/Fozyhh)
* [Caterina Motti](https://github.com/mttcrn)