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https://github.com/muhammadtalhasami/axi4_lite_interface
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
https://github.com/muhammadtalhasami/axi4_lite_interface
axi4 axi4-lite axi4-lite-interface axi4-lite-system-verilog axi4-protocol system-verilog verilator vivado
Last synced: 9 days ago
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This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
- Host: GitHub
- URL: https://github.com/muhammadtalhasami/axi4_lite_interface
- Owner: muhammadtalhasami
- Created: 2024-05-03T08:07:29.000Z (8 months ago)
- Default Branch: main
- Last Pushed: 2024-05-04T09:22:03.000Z (8 months ago)
- Last Synced: 2024-11-06T10:13:45.734Z (about 2 months ago)
- Topics: axi4, axi4-lite, axi4-lite-interface, axi4-lite-system-verilog, axi4-protocol, system-verilog, verilator, vivado
- Language: SystemVerilog
- Homepage: https://github.com/muhammadtalhasami/Axi4_lite_interface
- Size: 104 KB
- Stars: 1
- Watchers: 1
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# AXI4_LITE_INTERFACE
# INTRO
Advanced eXtensible Interface 4 (AXI4) is a family of buses defined as part of the fourth generation of the ARM Advanced Microcontroler Bus Architectrue (AMBA) standard. AXI was first introduced with the third generation of AMBA, as AXI3, in 1996.
The AMBA specification defines 3 AXI4 protocols:
AXI4: A high performance memory mapped data and address interface. Capable of Burst access to memory mapped devices.
AXI4-Lite: A subset of AXI, lacking burst access capability. Has a simpler interface than the full AXI4 interface.
AXI4-Stream: A fast unidirectional protocol for transfering data from master to slave.
Use in Xilinx-Based designs
Xilinx Vivado helps in the creation of custom IP with AXI4 interfaces. These can be connected to the Zynq’s Proccessing System or to other devices. This Document will cover the operation of the AXI4-Lite interface, which is convenient for implementing memory mapped registers.
# TRANSACTION AND CHANNELS
THere are two transactions Read and Wirte transaction
The AXI4-Lite interface consists of five channels: Read Address, Read Data, Write Address, Write Data, and Write Response.
# AXI4 read transaction
**1):** Read Address channel
**2):** Read Data channel
# AXI4 write transaction
**1):** Write Address channel
**2):** wite Data channel
**3):** write Response channel
# HAND SHAKE PROCESS
All five transaction channels use the same VALID/READY handshake process to transfer address, data, and control information. This two-way flow control machanism means both the master and slave can control the rate at which the information moves between master and slave. The information source generates the VALID signal to indicate when the address, data or control information is available. The information destination generates the READY signal to indicate that it can accept the information. The handshake completes if both VALID and READY signals in a channel are asserted during a rising clock edge.
# VIVADO_WAVEFORM
# VERILATOR_WAVEFORM
# SCHEMATIC VIEW
# HOW TO USE
**1):** clone my repo
```
git clone https://github.com/muhammadtalhasami/Axi4_lite_interface
```
**2):** Follow this
For Vivado
```
https://github.com/muhammadtalhasami/Axi4_lite_interface/tree/main/AXI4_LITE_VIVADO/AXI4_LITE_INTERFACE.srcs
Here you will get the test bench and source code
```
For verilator
Run make to compile the code and then run make waves to generate a wave form:
```
make
make waves
```
# INSTRUCTORS
. [Zeeshan Rafique](https://github.com/zeeshanrafique23)
. [Sajjad Ahmed](https://github.com/sajjadahmed677)
. [Zain Ali](https://github.com/ZAIN-ALI-02)
. [Ammar Bin Amir](https://github.com/Ammar-Bin-Amir)
# RESOURCE
For more information on AXI4 Lite Protocol
click here👉[RealDigital](https://www.realdigital.org/doc/a9fee931f7a172423e1ba73f66ca4081)
# CONTRIBUTOR
. [Hajra Kamran](https://github.com/HajraKamran)
Contributions are welcome! Feel free to fork this repository, make improvements, and submit pull requests.