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https://github.com/mummanajagadeesh/improve
Image processing using Verilog
https://github.com/mummanajagadeesh/improve
digital digital-image-processing edge-detection edge-detection-algorithms filtering-algorithm filters geometric-transformations hdl image-filters image-processing masks morphological-operators noise-reduction verilog verilog-hdl
Last synced: 6 days ago
JSON representation
Image processing using Verilog
- Host: GitHub
- URL: https://github.com/mummanajagadeesh/improve
- Owner: Mummanajagadeesh
- Created: 2024-12-09T07:36:56.000Z (2 months ago)
- Default Branch: main
- Last Pushed: 2024-12-19T14:58:04.000Z (about 2 months ago)
- Last Synced: 2024-12-19T15:47:58.964Z (about 2 months ago)
- Topics: digital, digital-image-processing, edge-detection, edge-detection-algorithms, filtering-algorithm, filters, geometric-transformations, hdl, image-filters, image-processing, masks, morphological-operators, noise-reduction, verilog, verilog-hdl
- Language: Verilog
- Homepage:
- Size: 13.7 MB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE