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https://github.com/myriadrf/LimeSDR-Mini_GW
LimeSDR-Mini board FPGA project
https://github.com/myriadrf/LimeSDR-Mini_GW
Last synced: 2 months ago
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LimeSDR-Mini board FPGA project
- Host: GitHub
- URL: https://github.com/myriadrf/LimeSDR-Mini_GW
- Owner: myriadrf
- License: apache-2.0
- Created: 2017-07-01T11:42:38.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2022-08-27T13:43:30.000Z (about 2 years ago)
- Last Synced: 2024-06-03T00:36:12.795Z (4 months ago)
- Language: Verilog
- Homepage:
- Size: 55 MB
- Stars: 55
- Watchers: 12
- Forks: 40
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- Changelog: Changelog.txt
- License: COPYING
Awesome Lists containing this project
README
# LimeSDR-Mini FPGA gateware
This repository contains the FPGA gateware project for the LimeSDR-Mini v1.2 board.
The gateware can be built with the free version of the Altera Quartus (Version 15.1.2 Build 193 02/01/2016 SJ Lite Edition) tools.
## Branches
This repository contains the following hardware-specific branches:
* master:
* Compiled gateware file for Hardware Revision 1v2 is LimeSDR-Mini_bitstreams/LimeSDR-Mini_lms7_trx_HW_1.2.pof.
* Other branches will be removed later.
## LicensingPlease see the COPYING file(s). However, please note that the license terms stated do not extend to any files provided with the Altera design tools and see the relevant files for the associated terms and conditions.