https://github.com/namberino/vsap-1

Implementation of the SAP-1 in FPGA
https://github.com/namberino/vsap-1

Last synced: 3 months ago
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Implementation of the SAP-1 in FPGA

• Host: GitHub
• URL: https://github.com/namberino/vsap-1
• Owner: namberino
• License: bsd-2-clause
• Created: 2024-02-23T02:55:36.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-05-21T13:54:35.000Z (about 1 year ago)
• Last Synced: 2025-01-20T18:24:14.056Z (4 months ago)
• Language: Verilog
• Homepage: https://namberino.github.io/posts/2024/02/8-bit-computer-in-fpga/
• Size: 171 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# VSAP-1: A processor based on the SAP-1 made in FPGA

This is a computer implemented using Verilog

Currently, this computer can perform addition and subtraction on integers

We can program this computer using the [program.bin](program.bin) file

To understand how the computer works, reference [doc.md](/docs/doc.md)

I used [Apio](https://github.com/FPGAwars/apio) as my FPGA toolbox

Simulation (done with [GTKWave](https://gtkwave.sourceforge.net/)):

![waveform](docs/waveform.png)

> Note: Check the [example_program.md](docs/example_program.md) to learn how to program this computer

References: 

- [Ben Eater's 8-bit computer series](https://www.youtube.com/playlist?list=PLowKtXNTBypGqImE405J2565dvjafglHU)

- [Digital Computer Electronics](https://www.amazon.com/Digital-Computer-Electronics-Jerald-Malvino-dp-0074622358/dp/0074622358/ref=dp_ob_title_bk)

- [SAP-1 Implementation Report](https://drive.google.com/file/d/17fH-JBU5OX_4AG123AO47y879YxzmDwX/view)