https://github.com/nambers/0dmips
[WIP] in-order 5-stages pipeline MIPS64r6el SoC implementation with peripheral components, simulated with verilator
https://github.com/nambers/0dmips
mips64 systemverilog verilator
Last synced: 20 days ago
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[WIP] in-order 5-stages pipeline MIPS64r6el SoC implementation with peripheral components, simulated with verilator
- Host: GitHub
- URL: https://github.com/nambers/0dmips
- Owner: Nambers
- License: mit
- Created: 2024-10-03T22:08:57.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-07-17T18:55:53.000Z (6 months ago)
- Last Synced: 2025-07-17T22:16:52.491Z (6 months ago)
- Topics: mips64, systemverilog, verilator
- Language: C++
- Homepage:
- Size: 3.08 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE