https://github.com/nambers/mips64
[WIP] 5-stage pipeline MIPS64 SoC implementation with peripheral components, simulated with verilator
https://github.com/nambers/mips64
mips64 systemverilog verilator
Last synced: 10 months ago
JSON representation
[WIP] 5-stage pipeline MIPS64 SoC implementation with peripheral components, simulated with verilator
- Host: GitHub
- URL: https://github.com/nambers/mips64
- Owner: Nambers
- License: mit
- Created: 2024-10-03T22:08:57.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-01-24T23:24:31.000Z (12 months ago)
- Last Synced: 2025-01-25T00:23:40.258Z (12 months ago)
- Topics: mips64, systemverilog, verilator
- Language: SystemVerilog
- Homepage:
- Size: 873 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# MIPS64
## Dependenices
- `mips64-linux-gnu` toolchains(`as` and `objdump`), they're under [mips64-linux-gnu-binutils](https://aur.archlinux.org/packages/mips64-linux-gnu-binutils) in Arch.
- \[OPTIONAL\] `mips64-linux-gcc` if you like to write C directly.
- `verilator` for simulations.
- \[OPTIONAL\] `sdl3` for any simulation with VGA output.
## How to run
1. `./scripts/cloneGoogleTest.sh` to build gTest.
2. `make runtest` to run all tests.
3. `make ` (e.g. `make alu`) to run specific test under tests folder, or `make runtest` to run all tests.
4. `make example_asm/` (e.g. `make example_asm/fabonacci`) to compile assembly into binary.
5. `make ` (e.g. `make core`) to run the simulation of compiled binary.