https://github.com/nazago/risc-v-in-tl-verilog

https://github.com/nazago/risc-v-in-tl-verilog

Last synced: about 2 months ago
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• Host: GitHub
• URL: https://github.com/nazago/risc-v-in-tl-verilog
• Owner: nazago
• License: mit
• Created: 2022-06-07T11:10:22.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2022-06-07T11:14:02.000Z (over 2 years ago)
• Last Synced: 2024-09-17T20:58:02.231Z (3 months ago)
• Size: 5.86 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# RISC-V-in-TL-Verilog

This is a project made to make a RISC-V architecture and know more about TL-verilog. In the future, I am planning to expand it with branch predictions and other techniques used in moder architectures.

Took inspiration and guidance from https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv.