https://github.com/nellyw8/verireason
This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
https://github.com/nellyw8/verireason
ai4eda code-generation eda hardware hdl large-language-models llama llm openr1 qwen reasoning reasoning-language-models reinforcement-learning research-paper rlhf testbench-generator-verilog verilog verilog-code verilog-hdl verilogeval
Last synced: 1 day ago
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This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
- Host: GitHub
- URL: https://github.com/nellyw8/verireason
- Owner: NellyW8
- Created: 2025-05-17T01:39:13.000Z (about 1 month ago)
- Default Branch: main
- Last Pushed: 2025-06-09T23:42:34.000Z (11 days ago)
- Last Synced: 2025-06-20T02:02:12.708Z (1 day ago)
- Topics: ai4eda, code-generation, eda, hardware, hdl, large-language-models, llama, llm, openr1, qwen, reasoning, reasoning-language-models, reinforcement-learning, research-paper, rlhf, testbench-generator-verilog, verilog, verilog-code, verilog-hdl, verilogeval
- Language: Python
- Homepage: https://nellyw8.github.io/VeriReason/
- Size: 272 KB
- Stars: 5
- Watchers: 2
- Forks: 1
- Open Issues: 0
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Metadata Files:
- Readme: README.MD