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https://github.com/nic30/hdlconvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
https://github.com/nic30/hdlconvertor
antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser
Last synced: about 11 hours ago
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Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
- Host: GitHub
- URL: https://github.com/nic30/hdlconvertor
- Owner: Nic30
- License: mit
- Created: 2016-06-28T13:19:49.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2024-09-03T22:12:39.000Z (5 months ago)
- Last Synced: 2025-01-10T18:12:14.403Z (8 days ago)
- Topics: antrl4, fpga, parser, python, systemverilog, systemverilog-parser, verilog, verilog-parser, vhdl, vhdl-parser
- Language: C++
- Homepage:
- Size: 14.5 MB
- Stars: 285
- Watchers: 22
- Forks: 68
- Open Issues: 35
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# hdlConvertor
[](https://circleci.com/gh/Nic30/hdlConvertor)
[](https://ci.appveyor.com/project/nic30/hdlconvertor)
[](http://badge.fury.io/py/hdlConvertor)
[](https://img.shields.io/pypi/pyversions/hdlConvertor.svg)
[](https://gitter.im/hdlConvertor/community?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
[](https://coveralls.io/github/Nic30/hdlConvertor?branch=master)(generated code)
This library is a System Verilog and VHDL parser, preprocessor and code generator for Python/C++.
It contains:
* ANTLR4 generated VHDL/(System) Verilog parser with full language support.
* Convertors from raw VHDL/SV AST to universal HDL AST ([hdlConvertor::hdlAst](https://github.com/Nic30/hdlConvertor/tree/master/include/hdlConvertor/hdlAst) and it's [python equivalent](https://github.com/Nic30/hdlConvertorAst/tree/master/hdlConvertorAst/hdlAst).).
* Convertors from this HDL AST [to SV/VHDL/JSON](https://github.com/Nic30/hdlConvertorAst/tree/master/hdlConvertorAst/to) and other formats.
* Compiler focused [utils](https://github.com/Nic30/hdlConvertorAst/tree/master/hdlConvertorAst/translate) for manipulation with HDL AST.
* HdlAstVisitor, id resolution, sensitivity detection, vhdl <-> verilog type conversion, ...
### Supported languages:
* [IEEE 1076-2008 (VHDL 2008)](https://ieeexplore.ieee.org/document/4772740) and all previous standard, (currently without `tool_directive` and `PSL`)
* [IEEE 1076-2019] WIP
* [IEEE 1800-2017 (SystemVerilog 2017)](https://ieeexplore.ieee.org/document/8299595) and all previous standards.
## Installation
Linux:
Installing dependencies (Ubuntu 20.10)
```
# we recommend to use gcc>=9, Visual Studio 2017 or equivalent
sudo apt install build-essential uuid-dev cmake default-jre python3 python3-dev python3-pip libantlr4-runtime-dev antlr4 ninja-build
```
Installing this library
```
# note this may be older version than you see in repo
sudo pip3 install hdlConvertor
# or download repository and run
sudo pip3 install --upgrade --force-reinstall --no-cache-dir git+https://github.com/Nic30/hdlConvertorAst.git
sudo pip3 install -r requirements.txt
sudo python3 setup.py install
# if you are using version from git rather uninstall
# old library first if required
# sudo pip3 uninstall hdlConvertor
```
Installer also supports other options which may be usefull
```
python setup.py install --prefix /tmp/python_install/ --build-type Debug -- -DANTLR_JAR_LOCATION=/antlr-4.7.1-complete.jar -- VERBOSE=1
```
You can also install only C++ library/generate .deb package (nothing specific, just normal cmake-based library)
```
mkdir build && cd build
cmake .. && cmake . --build
cpack # to generate .deb package
```
Windows:
Take a look at appveyor.yml and [doc/windows_installation_and_build.rst](doc/windows_installation_and_build.rst). It is required to download antlr4 first and have visual studio or other c++ compiler installed.
## Usage
The HDL AST (the parsed code) is represented by objects from `hdlConvertor.hdlAst`. Parsing and code modification is straightforward, as you can see in following example [](https://mybinder.org/v2/gh/Nic30/hdlConvertor/master?filepath=notebooks%2F01_parse_and_dump.ipynb)
### Similar projects:
(Tell us If you know about some other project!)
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* [HDL_ANTLR4](https://github.com/denisgav/HDL_ANTLR4) - C# projects that use ANTLR4 library to analyse VHDL and Verilog code
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* [rust_hdl](https://github.com/kraigher/rust_hdl) - rust vhdl 2008 parser
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* [sv-parser](https://github.com/dalance/sv-parser) - Rust, SystemVerilog parser library fully complient with IEEE 1800-2017
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* [verilog-parser](https://github.com/ben-marshall/verilog-parser) - A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
* [vbpp](https://github.com/balanx/vbpp) - C, Verilog PreProcessor
* [tree-sitter-verilog](https://github.com/tree-sitter/tree-sitter-verilog) - JS, Verilog grammar for tree-sitter
* [Verilog-Perl](https://metacpan.org/pod/Verilog-Perl)
* [vpp.pl](https://www.beyond-circuits.com/wordpress/vpp-pl-man-page/) - verilog preprocessor with integrated Perl
* [sv2v](https://github.com/zachjs/sv2v)- Haskell, SystemVerilog to Verilog
* [Surelog](https://github.com/alainmarcel/Surelog) - C++, System Verilog 2017 Pre-processor and parser
* [UHDM](https://github.com/alainmarcel/UHDM) - rust, universal hardware data model
* [HDLParserSharp](https://github.com/Aperture-Electronic/HDLParserSharp) - C#, VHDL/SV -> universal AST