https://github.com/nightmachinery/toy_mips_cpu
An implementation of a simple, non-pipelining CPU using gate-level Verilog
https://github.com/nightmachinery/toy_mips_cpu
Last synced: 5 months ago
JSON representation
An implementation of a simple, non-pipelining CPU using gate-level Verilog
- Host: GitHub
- URL: https://github.com/nightmachinery/toy_mips_cpu
- Owner: NightMachinery
- Created: 2020-05-07T10:41:50.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2020-05-07T10:43:37.000Z (about 6 years ago)
- Last Synced: 2024-12-31T17:48:09.056Z (over 1 year ago)
- Language: Verilog
- Homepage:
- Size: 7.6 MB
- Stars: 0
- Watchers: 3
- Forks: 0
- Open Issues: 0
-
Metadata Files: