https://github.com/nikhilrout/ntt-fpga
Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-based PQC on FPGAs
https://github.com/nikhilrout/ntt-fpga
fpga homomorphic-encryption lattice-based-crypto number-theoretic-transform post-quantum-cryptography
Last synced: 5 months ago
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Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-based PQC on FPGAs
- Host: GitHub
- URL: https://github.com/nikhilrout/ntt-fpga
- Owner: NikhilRout
- License: mit
- Created: 2024-09-11T13:06:31.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2025-02-19T08:53:47.000Z (over 1 year ago)
- Last Synced: 2025-04-13T12:53:50.639Z (about 1 year ago)
- Topics: fpga, homomorphic-encryption, lattice-based-crypto, number-theoretic-transform, post-quantum-cryptography
- Language: Verilog
- Homepage:
- Size: 1.36 MB
- Stars: 9
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# NTT_FPGA
Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT), utilizing modulo arithmetic, for developing lattice-based Post Quantum Cryptography (PQC) and Homomorphic Encryption (HE) on FPGAs as desribed in the paper
> A. Satriawan, I. Syafalni, R. Mareta, I. Anshori, W. Shalannanda and A. Barra, "Conceptual Review on Number Theoretic Transform and Comprehensive Review on Its Implementations," in IEEE Access, vol. 11, pp. 70288-70316, 2023, doi: 10.1109/ACCESS.2023.3294446
# Worked Out Example
## Number Theoretic Transform (NTT)
A four-point NTT structure with **ψ** = 1925 in the ring **Z**7681 is considered. A Cooley-Tukey butterfly unit based fast-NTT requires log2(n) stages. This implies our example shall need 2 stages\. Inputs are in Normal order, Outputs are in Bit-reversed Order\
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## Inverse Number Theoretic Transform (INTT)
Likewise a four-point INTT structure based on Gentleman-Sande Butterfly units shall require 2 stages. Inputs are in Bit-reversed Order, Outputs are in Normal order\
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