https://github.com/nikhilrout/verilog-dsd
Verilog implementations of fundamental combinational and sequential circuits (with testbenches)
https://github.com/nikhilrout/verilog-dsd
verilog verilog-hdl
Last synced: 7 months ago
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Verilog implementations of fundamental combinational and sequential circuits (with testbenches)
- Host: GitHub
- URL: https://github.com/nikhilrout/verilog-dsd
- Owner: NikhilRout
- License: mit
- Created: 2023-09-21T18:12:57.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2025-02-23T15:01:39.000Z (8 months ago)
- Last Synced: 2025-02-23T16:18:38.466Z (8 months ago)
- Topics: verilog, verilog-hdl
- Language: Verilog
- Homepage:
- Size: 1.75 MB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# verilog-dsd
Verilog implementations of fundamental combinational and sequential circuits (with testbenches)
## About
Starting out with Verilog during my first digital systems design class, I couldn't find a comprehensive Verilog guide with multiple examples all in one resource. So I decided to create this reference repository consolidating all my Verilog code as I progressed in class and my own study. It includes the dataflow, structural, and behavioral modeling of Verilog code for a broad range of fundamental combinational and sequential circuits, complete with corresponding testbenches
## Projects (Combinational)
### Adders and Subtractors
1. Half Adder
2. Full Adder
3. Half Subtractor
4. Full Subtractor
5. 4-bit Ripple Carry Adder, n-Bit
6. Combined Parallel Adder/Subtractor
7. Carry Look-Ahead Adder
### Decoders/Encoders
1. Decoder (2:4)
2. Decoder (3:8)
3. Encoder (4:2)
4. Encoder (Octal:Binary)
6. Priority Encoder (4:2)
### Multiplexers/Demultiplexers
1. Multiplexer (4:1)
2. Demultiplexer (1:8)
### Parity Gen/Check
1. Parity Generator
2. Parity Checker
### Multipliers
1. Array Multiplier
2. Booth Multiplier
3. LUT Multiplier
4. LUT Multiplier py code generator
5. Booth Algorithm 4-bit
### Misc
1. Basic Gates
2. Magnitude Comparator
3. Binary to Gray Code
4. Gray Code to Binary
5. Tri-State Buffers
6. Sign-Extender(9 to 16)
7. Switch-Level-Modeled Basic Gates
8. Reversible Full Adder
## Projects (Sequential)
### Latches
1. SR Latch
2. D Latch
### Flip-Flops
1. SR Flip-FLop
2. D Flip-Flop
3. JK Flip-Flop
4. T Flip-Flop
### Registers
1. SISO
2. SIPO
3. PISO
4. PIPO
### Counters
1. Asynchronous Counter
2. Synchronous Counter
3. Ring Counter
4. Johnson Counter
5. Gray Counter
### Finite State Machines
1. FSM Examples
2. Moore Sequence Detector
3. Mealy Sequence Detector
## Random Notes
### Choosing modeling style
• Boolean Expression → Dataflow\
• Logic Diagram → Structural\
• Truth Table → Behavioral
### EDAPlayground Settings
[EDAPlayground](http://www.edaplayground.com) is an application that includes an online IDE to simulate Verilog programs and a community project hub\
• Compiler: Icarus Verilog 0.9.7
• To open EPWave after run, include the lines ```$dumpfile("dump.vcd"); $dumpvars;``` at the start of the testbenches' inital block
### Errors/Updates/Contact
