https://github.com/nishit0072e/binary_input_fpga

A Verilog code on Binary input and display output in 7 segment display in FPGA
https://github.com/nishit0072e/binary_input_fpga

Last synced: 19 days ago
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A Verilog code on Binary input and display output in 7 segment display in FPGA

• Host: GitHub
• URL: https://github.com/nishit0072e/binary_input_fpga
• Owner: nishit0072e
• Created: 2023-02-24T08:31:04.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2023-02-24T11:45:44.000Z (almost 2 years ago)
• Last Synced: 2023-05-03T07:47:55.433Z (over 1 year ago)
• Language: HTML
• Size: 8.53 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0

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