https://github.com/nishit0072e/enc_dec_xor

8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.
https://github.com/nishit0072e/enc_dec_xor

Last synced: 4 days ago
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8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.

• Host: GitHub
• URL: https://github.com/nishit0072e/enc_dec_xor
• Owner: nishit0072e
• Created: 2023-10-11T17:19:41.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2023-10-11T19:34:18.000Z (about 1 year ago)
• Last Synced: 2023-10-12T04:15:11.887Z (about 1 year ago)
• Language: Verilog
• Size: 10.7 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
Block Diagram: 👇

![Block_diagram](https://github.com/nishit0072e/Enc_Dec_Xor/assets/65007263/1187f515-12f6-4706-81c3-cf6944c90f50)

RTL Design: 👇

![RTL](https://github.com/nishit0072e/Enc_Dec_Xor/assets/65007263/091a41e0-50aa-4f63-ad2e-d38f079b16e7)

Simulation Waveform: 👇

![Screenshot 2023-10-11 221430](https://github.com/nishit0072e/Enc_Dec_Xor/assets/65007263/782234d5-fb02-46ad-b883-7ffcf1bd304a)

# Enc_Dec_Xor

8:3 Encoder is used as input and  3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.