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https://github.com/nishit0072e/t_flipflop-using-vhdl
T FlipFlop is created with frequency divider in basys3 FPGA board of family Artix-7 with VHDL language
https://github.com/nishit0072e/t_flipflop-using-vhdl
Last synced: 4 days ago
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T FlipFlop is created with frequency divider in basys3 FPGA board of family Artix-7 with VHDL language
- Host: GitHub
- URL: https://github.com/nishit0072e/t_flipflop-using-vhdl
- Owner: nishit0072e
- Created: 2022-12-21T07:04:43.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2022-12-21T07:05:31.000Z (about 2 years ago)
- Last Synced: 2023-05-03T07:47:55.578Z (over 1 year ago)
- Size: 2.93 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0