https://github.com/niw/chisel_test
A simple Chisel test project for myself to learn Chisel and FPGA.
https://github.com/niw/chisel_test
chisel3 fpga orangecrab scala tinyfpga verilog
Last synced: 4 months ago
JSON representation
A simple Chisel test project for myself to learn Chisel and FPGA.
- Host: GitHub
- URL: https://github.com/niw/chisel_test
- Owner: niw
- Created: 2021-10-10T18:53:25.000Z (over 4 years ago)
- Default Branch: master
- Last Pushed: 2021-11-08T06:23:59.000Z (over 4 years ago)
- Last Synced: 2025-01-06T02:29:24.448Z (about 1 year ago)
- Topics: chisel3, fpga, orangecrab, scala, tinyfpga, verilog
- Language: Scala
- Homepage:
- Size: 18.6 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
Chisel Test
===========
A simple project for myself to learn Chisel and FPGA.
Supports [TinyFPGA BX](https://github.com/tinyfpga/TinyFPGA-BX) and [OrangeCrab](https://github.com/orangecrab-fpga/orangecrab-hardware) boards.
Build tool are required separately.
- [sbt](https://www.scala-sbt.org/)
- [yosys](https://github.com/YosysHQ/yosys)
- [icestorm](https://github.com/YosysHQ/icestorm) (for TinyFPGA BX, iCE40)
- [prjtrellis](https://github.com/YosysHQ/prjtrellis) (for OrangeCrab, ECP5)
- [nextpnr](https://github.com/YosysHQ/nextpnr)
- [tinyprog](https://github.com/tinyfpga/TinyFPGA-Bootloader/tree/master/programmer) (for TinyFPGA BX)
- [dfu-util](http://dfu-util.sourceforge.net/) (for OrangeCrab)
- [verilator](https://www.veripool.org/verilator/) (for unit tests)
Usage
-----
To build a bitstream for a specific top module, simply `make` with `TOP_MODULE`.
Where `BOARD` can be `tinyfpgabx` or `orangecrab`.
```
make BOARD=... TOP_MODULE=...
```
For TinyFPGA BX, to program bitstream, connect device to USB then use `prog` task.
```
make BOARD=tinyfpgabx TOP_MODULE=... prog
```
For OrangeCrab, to dfu bitstream, connect device to USB, then use `dfu` task.
```
make BOARD=orangecrab TOP_MODULE=... dfu
```