https://github.com/nsailor/feather

A single cycle processor implementing a subset of the ARMv7 ISA.
https://github.com/nsailor/feather

armv7 computer-architecture digital-design systemverilog verilator

Last synced: 19 days ago
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A single cycle processor implementing a subset of the ARMv7 ISA.

• Host: GitHub
• URL: https://github.com/nsailor/feather
• Owner: nsailor
• Created: 2018-07-30T22:42:48.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2018-09-11T20:45:08.000Z (about 6 years ago)
• Last Synced: 2023-08-03T08:06:51.185Z (over 1 year ago)
• Topics: armv7, computer-architecture, digital-design, systemverilog, verilator
• Language: SystemVerilog
• Size: 147 KB
• Stars: 1
• Watchers: 1
• Forks: 1
• Open Issues: 2

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