https://github.com/nullobject/riscv-ulx3s
https://github.com/nullobject/riscv-ulx3s
Last synced: about 2 months ago
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- Host: GitHub
- URL: https://github.com/nullobject/riscv-ulx3s
- Owner: nullobject
- Created: 2025-06-06T08:24:49.000Z (9 months ago)
- Default Branch: main
- Last Pushed: 2025-07-13T11:25:24.000Z (8 months ago)
- Last Synced: 2025-07-13T12:44:38.967Z (8 months ago)
- Language: Verilog
- Size: 161 KB
- Stars: 0
- Watchers: 0
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# riscv-ulx3s
## Getting Started
Install prerequisites:
```sh
sudo apt-get install autoconf automake autotools-dev curl python3 python3-pip python3-tomli libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev libslirp-dev
```
Build and install RISC-V toolchain:
```sh
gh repo clone riscv-collab/riscv-gnu-toolchain
cd riscv-gnu-toolchain
./configure --prefix=/opt/riscv32i --with-arch=rv32i
make -j$(nproc)
```
Build project and program the FPGA:
```sh
make program
```