https://github.com/nxbyte/ARM-LEGv8

Verilog Implementation of an ARM LEGv8 CPU
https://github.com/nxbyte/ARM-LEGv8

arm arm-legv8-simulator forwarding-unit hazard-detection hennessy isa ldr legv8-arm multi-cycle patterson pipeline-cpu single-cycle verilog vivado xilinx

Last synced: 6 months ago
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Verilog Implementation of an ARM LEGv8 CPU

• Host: GitHub
• URL: https://github.com/nxbyte/ARM-LEGv8
• Owner: nxbyte
• License: mit
• Created: 2018-04-22T04:59:40.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2018-10-03T02:19:46.000Z (over 6 years ago)
• Last Synced: 2024-08-08T13:15:18.481Z (10 months ago)
• Topics: arm, arm-legv8-simulator, forwarding-unit, hazard-detection, hennessy, isa, ldr, legv8-arm, multi-cycle, patterson, pipeline-cpu, single-cycle, verilog, vivado, xilinx
• Language: Verilog
• Homepage:
• Size: 3.96 MB
• Stars: 96
• Watchers: 5
• Forks: 29
• Open Issues: 2

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