https://github.com/nyuichi/chisel-uart
Uart module written in chisel
https://github.com/nyuichi/chisel-uart
Last synced: about 1 month ago
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Uart module written in chisel
- Host: GitHub
- URL: https://github.com/nyuichi/chisel-uart
- Owner: nyuichi
- Created: 2015-05-17T06:36:12.000Z (about 10 years ago)
- Default Branch: master
- Last Pushed: 2016-02-19T12:46:53.000Z (about 9 years ago)
- Last Synced: 2025-03-27T13:46:20.551Z (about 2 months ago)
- Language: Scala
- Size: 10.7 KB
- Stars: 13
- Watchers: 4
- Forks: 3
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
UART for chisel
===============
Following classes are provided:
* UartTx
* UartRx
* Uart
* BufferedUartTx
* BufferedUartRx
* BufferedUart
In buffering mode, when the number of data coming from rxd signal exceeds the buffering capacity, uart modules discard the byte without any signals.