https://github.com/obijuan/risc-v-fpga
RISC-V CPU for OpenFPGAs, in Icestudio
https://github.com/obijuan/risc-v-fpga
Last synced: 3 months ago
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RISC-V CPU for OpenFPGAs, in Icestudio
- Host: GitHub
- URL: https://github.com/obijuan/risc-v-fpga
- Owner: Obijuan
- License: gpl-3.0
- Created: 2019-09-10T15:34:43.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2024-06-02T16:51:58.000Z (about 1 year ago)
- Last Synced: 2025-03-22T17:44:20.718Z (4 months ago)
- Language: Assembly
- Size: 14.4 MB
- Stars: 91
- Watchers: 13
- Forks: 14
- Open Issues: 4
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# RISC-V-FPGA
RISC-V CPU for OpenFPGAs, in Icestudio
## Quick start
* Open the **soc-demo.ice** file with Icestudio 12 or higher
* Connect the Alhambra-II board (or compatible) and upload the design
* It will take around 1 min to sinthesize and upload to the board
* The system is ready for executing your firmware!
### Testing the firmaware in C
* go to the firmware/soc-demo/src-c folder
* Execute make (It is assumed that you already have the risc-v tools installed)
* You should see a binary counter in the LEDs
* If you open a serial terminal (115200 bauds) you will see messages
* In this [youtube video](https://www.youtube.com/watch?v=mv1SFoqzZWY) you can see it in action!
* Pressing the "1" key will reset the counter and show the intial message again
### Testing the firmware in asm
* go to the firmware/soc-demo/src-asm folder
* Execute make
* You should see a value in the LEDs
## Credits
It is based on the picorv32 by Clifford Wolf
https://github.com/cliffordwolf/picorv32
## SOCs for the RARs simulator
There are two socs for using with the RARs simulador:
* soc-rars-MMIO-1-port.ice: It have no uart and 1 output port at address 0xFFFF0000, connected to the LEDs
* soc-rars-MMIO-2-ports.ice: The previous soc plus one additional output port, connected to the D0-D7 pins in the Alhambra II board
In the firmware/soc-rars-MMIO-1/rars and firmware/soc-rars-MMIO-2/rars folderS there are examples for trying. Open them with the RARs simulator, assemble and dump the code into a .bin file. Then flash it into the FPGA with iceprog tool:
```
iceprog -o 1M file.bin
```
or [apio](https://github.com/FPGAwars/apio):
```
apio raw "iceprog -o 1M file.bin"
```