https://github.com/octcarp/sustech_cs202-organization_2023s_project-cpu
(Verilog+MIPS+FPGA MINISYS) (121/100): Single Cycle CPU: Our project of CS202 2023 Spring: Computer Organization, SUSTech. Taught by Prof. Jin ZHANG.
https://github.com/octcarp/sustech_cs202-organization_2023s_project-cpu
cpu cs202 fpga sustech verilog
Last synced: 2 months ago
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(Verilog+MIPS+FPGA MINISYS) (121/100): Single Cycle CPU: Our project of CS202 2023 Spring: Computer Organization, SUSTech. Taught by Prof. Jin ZHANG.
- Host: GitHub
- URL: https://github.com/octcarp/sustech_cs202-organization_2023s_project-cpu
- Owner: OctCarp
- License: mit
- Created: 2023-05-12T11:43:10.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2024-03-22T06:48:10.000Z (about 1 year ago)
- Last Synced: 2025-02-09T06:28:51.051Z (4 months ago)
- Topics: cpu, cs202, fpga, sustech, verilog
- Language: SystemVerilog
- Homepage:
- Size: 18.7 MB
- Stars: 8
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# SUSTech_CS202-Organization_2023s_Project-CPU
Single Cycle CPU: Our Project of CS202 2023 Spring: Computer Organization, SUSTech.
We use [FPGA MINISYS 1-A](http://www.e-elements.com/product/show/id/1.shtml) to implement part of the [MIPS32 instruction set](https://mips.com/products/architectures/mips32-2/). Support simple bit operations and binary addition, subtraction, multiplication, and division functions.
Final score: 121/100.
### Project Information
You can check [docs folder](docs/) to see project requirement. And our project report in Chinese.
### Repo Structure
```
├─ASM_Minisys-1A
├─CPU_Verilog
├─docs
├─EDA_Xilinx
└─unused
```
- **ASM_Minisys-1A** : MIPS assembly file and binary file ,check `Readme` in this folder for more information.
- **CPU_Verilog** : Verilog file for this project.
- **docs** : Project requirement and our report.
- **EDA_Xilinx** : Some files for Xilinx EDA Vivado, check `Readme` in this folder for more information.
- **unused** : Some unused files, including [Verilog file for onlinejudge test](unused/OJ_backup/).
### Quick Start
Use [Vivado](https://www.xilinx.com/products/design-tools/vivado.html), select the device `xc7a100tfgg484-1`.
You can load [bitstream file](EDA_Xilinx/CPU_TOP_new.bit) directly, or:
1. Add the IP core in [`EDA_Xilinx/`](EDA_Xilinx/)
2. The RAM and ROM IP core loads the `.coe` file in [`EDA_Xilinx/`](EDA_Xilinx/) respectively
3. Add the Verilog file in [`CPU_Verilog/`](CPU_Verilog/)
4. Add the [pin constraint file](EDA_Xilinx/minisys_cons.xdc)
5. Use VIvado to simulate, synthesize, and then generate bitstream files
### Board information
For example, if you want to do scene 1 test case `001`:
1. Press Program Restart Button
2. Press UART Start Reprogram Button, then use UART to transmit [`sc1_new_version.txt`](ASM_Minisys-1A/uart_txt/sc1_new_version.txt)
3. Press Program Restart Button again to start the new program
4. Let "Test case ID Input" low 3 bits switch be `001` (`1` means on), then press Input confirm button
5. Let Binary Value Input low 8 bits be the number 1 you want to input, then press Input confirm button, the Binary Value Input display will show the number 1 in high 8 bits.
6. Let Binary Value Input low 8 bits be the number 2 you want to input, then press Input confirm button, the Binary Value Input display will show the number 2 in low 8 bits.
7. Press Input confirm button, then the led or keyboard will show the result.