https://github.com/oetr/asip-dsl
A domain-specific language for making ASIPs that will be converted into VHDL code for subsequently running them on FPGAs
https://github.com/oetr/asip-dsl
Last synced: 3 months ago
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A domain-specific language for making ASIPs that will be converted into VHDL code for subsequently running them on FPGAs
- Host: GitHub
- URL: https://github.com/oetr/asip-dsl
- Owner: oetr
- Created: 2014-12-18T13:33:52.000Z (over 11 years ago)
- Default Branch: interpreter
- Last Pushed: 2015-02-12T23:58:44.000Z (over 11 years ago)
- Last Synced: 2025-12-21T11:16:49.543Z (6 months ago)
- Language: Racket
- Size: 316 KB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.org