https://github.com/offlinemark/eece3324mips
(Mini) MIPS ISA implementation.
https://github.com/offlinemark/eece3324mips
Last synced: about 2 months ago
JSON representation
(Mini) MIPS ISA implementation.
- Host: GitHub
- URL: https://github.com/offlinemark/eece3324mips
- Owner: offlinemark
- Created: 2014-11-20T03:56:45.000Z (over 10 years ago)
- Default Branch: master
- Last Pushed: 2014-12-06T17:54:47.000Z (over 10 years ago)
- Last Synced: 2025-02-07T19:42:33.655Z (4 months ago)
- Language: Verilog
- Homepage:
- Size: 802 KB
- Stars: 2
- Watchers: 2
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README
Awesome Lists containing this project
README
# (Mini) MIPS ISA Implementation
Mark Mossberg
Northeastern University
EECE 3324: Computer Architecture
Professor Yunsi Fei
December 5, 2014
## Description
This is a miniature implementation of a single cycle MIPS processor
architecture, supporting the following instructions:
- add, addi, addiu, slt
- beq, j
- lw, sw
- hlt (artificial)
See REPORT.md for more information.
## Testing
`cpu_tb.v' is the main testbench to run, and was tested using a simulation
time of 15015 ns. `memory1.v' and `MinMax.hexdump' are provided testing
files.