https://github.com/ogvalt/hardware_design_course_mips_core

MIPS core describe on Verilog with some test provided
https://github.com/ogvalt/hardware_design_course_mips_core

Last synced: about 2 months ago
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MIPS core describe on Verilog with some test provided

• Host: GitHub
• URL: https://github.com/ogvalt/hardware_design_course_mips_core
• Owner: ogvalt
• Created: 2016-10-10T08:58:43.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2016-10-24T20:42:51.000Z (over 8 years ago)
• Last Synced: 2024-10-15T03:29:19.536Z (3 months ago)
• Language: Verilog
• Homepage:
• Size: 66.4 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# MIPS_core

MIPS core describe on Verilog with some test provided

Project was simulated using ModelSim.

For simulating just compile all files in ModelSim 10.2c and run without optimization mips_tb.v

All asm file was created by using Mars 4.5. Be careful with this program. There are some bugs in Mars 4.5. Bugs are connected 

with counting of jump address via label in beq and bne command. In addition, there are no ROTR and ROTRV command in Mars 4.5.