https://github.com/ogvalt/melexis_internship_usart_design_and_verification

This is the USART verification project
https://github.com/ogvalt/melexis_internship_usart_design_and_verification

Last synced: about 2 months ago
JSON representation

This is the USART verification project

• Host: GitHub
• URL: https://github.com/ogvalt/melexis_internship_usart_design_and_verification
• Owner: ogvalt
• Created: 2016-10-20T13:08:12.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2016-10-20T13:10:53.000Z (over 8 years ago)
• Last Synced: 2024-10-15T03:29:19.523Z (3 months ago)
• Language: Verilog
• Size: 32.2 KB
• Stars: 2
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# USART_verify

This is the USART verification project