https://github.com/ogvalt/melexis_intership_lab

There are labs from Melexis laboratory
https://github.com/ogvalt/melexis_intership_lab

Last synced: about 2 months ago
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There are labs from Melexis laboratory

• Host: GitHub
• URL: https://github.com/ogvalt/melexis_intership_lab
• Owner: ogvalt
• Created: 2016-02-13T17:27:02.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2016-08-26T17:15:15.000Z (over 8 years ago)
• Last Synced: 2024-10-15T03:29:19.624Z (3 months ago)
• Language: Verilog
• Size: 402 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# melexis

There are labs from Melexis laboratory

First lab: ...

Second lab: consist of rtl descriptions of adder, subtractor, multiplier, bitwise nand, bitwise nor, ALU 

            and their parameterized version (plus testbench)

            

Third lab: consist of two fsm that describe traffic light and vending machine (testbenches are provided, plus answers of question)

Fourth lab: FIR filter