https://github.com/openlabun/riscvtranslator
https://github.com/openlabun/riscvtranslator
computer-architecture isa ricsv
Last synced: 7 months ago
JSON representation
- Host: GitHub
- URL: https://github.com/openlabun/riscvtranslator
- Owner: openlabun
- License: gpl-3.0
- Created: 2024-04-08T14:28:40.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2024-04-25T19:47:45.000Z (over 1 year ago)
- Last Synced: 2025-03-11T20:37:19.862Z (7 months ago)
- Topics: computer-architecture, isa, ricsv
- Language: JavaScript
- Size: 32.2 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
RISCV Translator
This tool is used on the Computer Architecture course at Universidad del Norte. It is used to translate MIPS instructions to Hexadecimal and viceversa. It also has a RISCV simulator that is still under development.
Funcionality:
1. From RISCV to Hexa
2. From Hexa to RISCV
3. Export and import Logisim RAM
4. RISCV Simulator (ongoing, add, addi, or, and , load, store are working)
List of supported instructions:
1. R (add, sub, and, or)
2. Load
3. Store
4. Branch (beq, bne)
5. Jump and link (jal)
To dockerize the app:
sudo docker build -t riscvtranslatori .
sudo docker run -d -it -p 5001:80 --restart unless-stopped --name riscvtranslator-app riscvtranslatori
To test (inside the app folder):
npm install --save-dev jest
npm install --save-dev jest-environment-jsdom
npm test
Shaddia Andrea Acuña Lara
Universidad del Norte 2024
GNU General Public License v3.0