https://github.com/osamamagdy/randomizer-module

A Randomizer design using VerilogHDL for Computers that takes one input and generate random values
https://github.com/osamamagdy/randomizer-module

Last synced: about 2 months ago
JSON representation

A Randomizer design using VerilogHDL for Computers that takes one input and generate random values

• Host: GitHub
• URL: https://github.com/osamamagdy/randomizer-module
• Owner: osamamagdy
• Created: 2020-05-15T07:59:56.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2020-05-15T08:00:04.000Z (over 4 years ago)
• Last Synced: 2023-03-11T15:57:57.298Z (almost 2 years ago)
• Language: Verilog
• Homepage:
• Size: 45.9 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0

Awesome Lists containing this project