https://github.com/oscc-ip/sdram
An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
https://github.com/oscc-ip/sdram
axi4 fpga sdram tapeout verilog
Last synced: 6 months ago
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An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
- Host: GitHub
- URL: https://github.com/oscc-ip/sdram
- Owner: oscc-ip
- Created: 2023-09-04T13:53:32.000Z (almost 3 years ago)
- Default Branch: master
- Last Pushed: 2025-05-11T14:27:28.000Z (about 1 year ago)
- Last Synced: 2025-05-11T15:24:21.129Z (about 1 year ago)
- Topics: axi4, fpga, sdram, tapeout, verilog
- Language: Scala
- Homepage: https://oscc-ip-sdram.readthedocs.io
- Size: 2.11 MB
- Stars: 17
- Watchers: 4
- Forks: 2
- Open Issues: 1
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Metadata Files:
- Readme: README.md
- Contributing: CONTRIBUTING.md
- License: LICENSE
- Code of conduct: CODE_OF_CONDUCT.md