https://github.com/osestic/74ls93_counter_integrated_circuit

Utilised System Verilog to create the 74LS93 Counter
https://github.com/osestic/74ls93_counter_integrated_circuit

digitallogicdesign electronics-design quartus-prime systemverilog vhdl

Last synced: 8 months ago
JSON representation

Utilised System Verilog to create the 74LS93 Counter

• Host: GitHub
• URL: https://github.com/osestic/74ls93_counter_integrated_circuit
• Owner: Osestic
• License: other
• Created: 2024-07-05T22:54:07.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-07-09T12:29:16.000Z (over 1 year ago)
• Last Synced: 2025-01-05T01:14:12.259Z (9 months ago)
• Topics: digitallogicdesign, electronics-design, quartus-prime, systemverilog, vhdl
• Language: VHDL
• Homepage:
• Size: 7.61 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

          
# 74LS93 Counter Integrated Circuit

![Screenshot 2024-07-05 141345](https://github.com/Osestic/Counter_74LS93/assets/42704298/05da086d-2aba-49e1-8fb0-91285aa36793)

![Screenshot 2024-07-05 141559](https://github.com/Osestic/Counter_74LS93/assets/42704298/c15d0f15-e87a-4226-8d87-023d36e0c7f3)

## Description

Counters such as 74ls93 are sequential circuits which can be designed with JK flip-flops and simulated using the Quartus application. These sequential circuits

go through a defined sequence of states upon the application of input impulses. 

​

## Built With







## Installation

Clone this repository and run the main project file, ```Counter_lab6_74ls93.qpf```, with the Quartus Prime software.

## Usage

After running the project file, click on RTL viewer as shown in the image below to see the design.

![image](https://github.com/Osestic/74LS93_Counter_Integrated_Circuit/assets/42704298/3a852e9b-5621-47dd-86cf-41a77100b2eb)

### Simulations ###

Run simulations on the design based on inputs by  following these steps.

1. Run the project file: ```Counter_lab6_74ls93.qpf```

2. Go to File >> New

3. Choose the University program under Verification/debugging files

   ![image](https://github.com/Osestic/74LS93_Counter_Integrated_Circuit/assets/42704298/a8b8c909-c8fc-4ac6-83ba-5d56f0bc776b)

4. Go to Edit >> Insert >> Insert Node or bus >> Node Finder >> List

5. Make sure to press okay when it appears after completing the steps

6. Choose the input states from the selection menu

7. Run the type of simulation you want from the options under Simulation

You can see some of the simulations I performed in ```simulation\qsim```. They end with the extensions ".vwf".

The simulations should look something like the image below.

![image](https://github.com/Osestic/74LS93_Counter_Integrated_Circuit/assets/42704298/dfed01ed-7550-47cf-aab2-9080b603212b)

## License

This project is licensed under the “Commons Clause” License Condition v1.0. See ```LICENSE``` for more information.

## How to Contribute

[![Contributor Covenant](https://img.shields.io/badge/Contributor%20Covenant-2.1-4baaaa.svg)](https://www.contributor-covenant.org/version/2/1/code_of_conduct/)

## Recommendations

- Incorporate the Counter 74LS93 in other digital logic and electronic designs and see how well it performs

- Allow other persons to use and test the design

- Act on the feedback accordingly