https://github.com/overflowcat/hdlbits

My HDLBits solutions
https://github.com/overflowcat/hdlbits

Last synced: 5 months ago
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My HDLBits solutions

• Host: GitHub
• URL: https://github.com/overflowcat/hdlbits
• Owner: OverflowCat
• Created: 2023-07-27T23:24:09.000Z (almost 3 years ago)
• Default Branch: top_module
• Last Pushed: 2023-08-01T15:16:59.000Z (almost 3 years ago)
• Last Synced: 2025-03-29T06:47:48.911Z (about 1 year ago)
• Language: Verilog
• Homepage:
• Size: 2.93 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# My [HDLBits](https://hdlbits.01xz.net/) solutions

## Contents

- Getting Started

  - [x] [Getting Started](./1%20Getting%20Started/step_one.v)

  - [x] [Output Zero](./1%20Getting%20Started/zero.v)

- Verilog Language

  - Basics

    - [x] [Simple wire](./2%20Verilog%20Language/1%20Basics/wire.v)

    - [x] [Four wires](./2%20Verilog%20Language/1%20Basics/wire4.v)

    - [x] [Inverter](./2%20Verilog%20Language/1%20Basics/notgate.v)

    - [x] [AND gate](./2%20Verilog%20Language/1%20Basics/andgate.v)

    - [x] [NOR gate](./2%20Verilog%20Language/1%20Basics/norgate.v)

    - [x] [XNOR gate](./2%20Verilog%20Language/1%20Basics/xnorgate.v)

    - [x] [Declaring wires](./2%20Verilog%20Language/1%20Basics/wire_decl.v)

    - [x] [7458 chip](./2%20Verilog%20Language/1%20Basics/7458.v)

  - Vectors

    - [x] [Vectors](./2%20Verilog%20Language/2%20Vectors/vector0.v)

    - [ ] [Vectors in more detail](./2%20Verilog%20Language/2%20Vectors/vector1.v)

    - [ ] [Vector part select](./2%20Verilog%20Language/2%20Vectors/vector2.v)

    - [ ] [Bitwise operators](./2%20Verilog%20Language/2%20Vectors/vectorgates.v)

    - [ ] Four-input gates