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https://github.com/pandeykartikey/riscy-processor
A 32-bit RISC processor implementation in verilog
https://github.com/pandeykartikey/riscy-processor
Last synced: 5 days ago
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A 32-bit RISC processor implementation in verilog
- Host: GitHub
- URL: https://github.com/pandeykartikey/riscy-processor
- Owner: pandeykartikey
- Created: 2017-09-26T18:06:55.000Z (about 7 years ago)
- Default Branch: master
- Last Pushed: 2018-10-02T20:47:30.000Z (about 6 years ago)
- Last Synced: 2023-08-08T05:34:47.645Z (over 1 year ago)
- Language: Verilog
- Homepage:
- Size: 253 KB
- Stars: 9
- Watchers: 4
- Forks: 4
- Open Issues: 1