https://github.com/parthpower/aes-fpga

AES implementation on FPGA
https://github.com/parthpower/aes-fpga

Last synced: 3 months ago
JSON representation

AES implementation on FPGA

• Host: GitHub
• URL: https://github.com/parthpower/aes-fpga
• Owner: parthpower
• License: apache-2.0
• Created: 2016-04-15T23:29:08.000Z (almost 10 years ago)
• Default Branch: master
• Last Pushed: 2016-04-17T22:14:41.000Z (almost 10 years ago)
• Last Synced: 2025-02-14T22:19:11.461Z (11 months ago)
• Language: VHDL
• Size: 15.6 KB
• Stars: 13
• Watchers: 2
• Forks: 3
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • License: LICENSE.md

Awesome Lists containing this project

README

          
# AES on FPGA (need a catchy name)

AES Encryption implementation on FPGA including standard interfaces for data transfer.

I will mostly use Xilinx ISE, Spartan6 XC6SLX9 of Numato Mimas V2 target.

That's it... 

Okay, I should document in more detail, but first VHDL.

Distributed under Apache 2.0 license