https://github.com/parthpower/axi_uartlite_pynq

PYNQ-Z1 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
https://github.com/parthpower/axi_uartlite_pynq

pynq-z1 python uart xilinx

Last synced: 9 months ago
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PYNQ-Z1 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx

• Host: GitHub
• URL: https://github.com/parthpower/axi_uartlite_pynq
• Owner: parthpower
• License: mit
• Created: 2017-11-17T09:18:54.000Z (about 8 years ago)
• Default Branch: master
• Last Pushed: 2021-06-16T00:38:06.000Z (over 4 years ago)
• Last Synced: 2025-03-25T22:51:33.332Z (10 months ago)
• Topics: pynq-z1, python, uart, xilinx
• Language: Tcl
• Homepage:
• Size: 15.9 MB
• Stars: 10
• Watchers: 1
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# axi_uartlite_pynq

[![Binder](https://mybinder.org/badge_logo.svg)](https://mybinder.org/v2/gh/parthpower/axi_uartlite_pynq/HEAD)

PYNQ Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx.

## UART Config

`Baud: 9600, RX Pin: PMODA 1, TX Pin: PMODA 2`

## Structure

	bits : Bitstream folder

	img : Image folder

	prj : Vivado project tcl

	src : Source folder (AXI uartlite class)

## Block Diagram

![Figure 1. Block Diagram](img/block.png)