https://github.com/patsaoglou/verilogblocktesting
Repository sharing some of the Verilog testbenches made for the Microprocessors Course lab homework
https://github.com/patsaoglou/verilogblocktesting
Last synced: 7 months ago
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Repository sharing some of the Verilog testbenches made for the Microprocessors Course lab homework
- Host: GitHub
- URL: https://github.com/patsaoglou/verilogblocktesting
- Owner: patsaoglou
- Created: 2025-01-04T20:31:00.000Z (9 months ago)
- Default Branch: main
- Last Pushed: 2025-02-07T07:59:01.000Z (8 months ago)
- Last Synced: 2025-02-07T08:31:53.446Z (8 months ago)
- Language: Verilog
- Size: 7.81 KB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# VerilogBlockTesting
Repository sharing some of the Verilog testbenches made with my mate Iatrakis Ioannis for the Microprocessors Course lab homework (Prof. Vasileios Tenentes).
Modules for the simple RISC-V CPU were supplied in the lab resources and we had to implement modifications and write new testbenches for the modified modules.