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https://github.com/pavlostzitzos/hdls-intro
SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial
https://github.com/pavlostzitzos/hdls-intro
verilog verilog-hdl verilog-testbenches vhdl
Last synced: 17 days ago
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SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial
- Host: GitHub
- URL: https://github.com/pavlostzitzos/hdls-intro
- Owner: PavlosTzitzos
- Created: 2023-01-07T17:25:35.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2024-02-12T13:59:05.000Z (11 months ago)
- Last Synced: 2024-11-06T00:12:40.593Z (2 months ago)
- Topics: verilog, verilog-hdl, verilog-testbenches, vhdl
- Language: SystemVerilog
- Homepage: https://pavlostzitzos.github.io/HDLs-intro/VerilogTutorial/
- Size: 20.1 MB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# Verilog-Code
This repository is an effort to make an introduction in SystemVerilog.
Start from Verilog folder first:
```mermaid
graph TD;
Verilog-->SystemVerilog;
Verilog-->Verilog-A;
Verilog-A-->Verilog-AMS;
SystemVerilog-->SystemVerilog-AMS;
Verilog-AMS-->SystemVerilog-AMS;
```
## To Do List
- [ ] fix the readme
- [ ] fix the site make it more readable if possible use a Framework
- [ ] add circuits to acompany the verilog snipets
- [ ] continue the tutorial
- [ ] add more resources
Basic differences
-----------------
Verilog (HDL | digital | Icarus Verilog)
- modules
- input/output/inout
- reg/wire
- always block
- assign
- testbenches(also modules)
- timescale
- always block for clk
- initial block
SystemVerilog (HDL | digital | Modelsim)
- modules
- input/output/inout (do not use: inout)
- reg/wire/logic (use: logic)
- always/ always_comb/always_ff blocks (do not use: always block)
- assign
- testbenches(also modules)
- timescale (do not use)
- always block for clk (prefer this)
- initial block
- task
Verilog-A (analog | LTSPICE)
- modules
- input/output/inout
- electrical
- analog / analog function blocks (prefer: analog block)
- assign
- testbench is a circuit (must be drawn)
Verilog-AMS (analog + digital | QUCS Studio)
- modules
- input/output/inout
- reg/wire/electrical
- always/ always_comb/always_ff blocks (do not use: always block)
- analog / analog function blocks (prefer: analog block)
- assign
- include :
- constants.vams
- disciplines.vams
- testbench is a circuit (must be drawn)
Sources that helped me starting learning HDL:
| No. | Sources | Verilog | SystemVerilog | UVM | VHDL | SystemC |
|:----:|:-------------------------------------------------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|
| 1 | https://fpgatutorial.com/ | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: |
| 2 | https://www.doulos.com/knowhow/ | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: |
| 3 | https://verificationguide.com/ | | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: |
| 4 | https://www.chipverify.com/ | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | |
| 5 | https://www.systemverilog.in/p/systemverilog-tutorial.html | | :heavy_check_mark: | :heavy_check_mark: | | |
| 6 | https://www.fpga4student.com/ | :heavy_check_mark: | | | :heavy_check_mark: | |
| 7 | https://github.com/JeffDeCola/my-verilog-examples | :heavy_check_mark: | | | | |
| 8 | https://systemverilogdesign.com/tag/multiply/ | :heavy_check_mark: | :heavy_check_mark: | | | |
| 9 | Digital Design , M. Morris Mano and Michael Ciletti , 6th Ed. | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | |
| 10 | Digital Design , William J. Dally and R. Curtis Harting | | :heavy_check_mark: | | | |
| ... | ... | ... | ... | ... | ... | ... |
Additional information:
1. Configuration instructions:
* No configurations necessary.
2. Installation instructions:
* I am using VisualStudioCode extensions:
+ https://github.com/mshr-h/vscode-verilog-hdl-support
+ https://www.wavetrace.io/
* Also I work with Icarus Verilog:
+ official site: http://iverilog.icarus.com/
+ download for windows: https://sourceforge.net/projects/iverilog/
+ other guides: https://iverilog.fandom.com/wiki/Installation_Guide (old)
+ new : https://steveicarus.github.io/iverilog/index.html
3. Operating instructions:
* Add Icarus Verilog to PATH.
* Always use flag: -g2012
4. A file manifest (list of files included):
Verilog
> intro
> tutorial
Verilog-A
> intro
> tutorial
Verilog-AMS
> intro
> tutorial
SystemVerilog
> course-material
> tutorial
> projects
5. Copyright and licensing information:
* See sources table.
6. Contact information:
* git
* mail
7. Known bugs:
* No bugs yet.
8. Troubleshooting:
* See each folder.
9. ToDo list:
- [ ] Fix folders
- [ ] Add simple examples
- [ ] add basic modules
- [ ] add comments
- [ ] add testbenches with multiple tests and add explaination
- [ ] complete the readme files
- [ ] find projects and create folders with readme files explaining the project