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https://github.com/pbrit/hack-verilog
Verilog implementation of Hack CPU from Nand2Tetris
https://github.com/pbrit/hack-verilog
Last synced: about 1 month ago
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Verilog implementation of Hack CPU from Nand2Tetris
- Host: GitHub
- URL: https://github.com/pbrit/hack-verilog
- Owner: pbrit
- Created: 2015-06-19T05:33:16.000Z (over 9 years ago)
- Default Branch: master
- Last Pushed: 2015-07-31T13:20:23.000Z (over 9 years ago)
- Last Synced: 2024-04-21T12:34:16.432Z (9 months ago)
- Language: Verilog
- Size: 148 KB
- Stars: 2
- Watchers: 2
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# Hack-verilog
## Combinational
Module | Behavior | Structure | Test coverage
------ | :------: | :-------: | :-----------:
Mux8Way16 | X | X | X
Mux16 | X | X | X
Mux4Way16 | X | X | X
Mux | X | X | X
DMux | X | X | X
And16 | X | X | X
DMux4Way | X | X | X
Decoder2 | X | X | X
Not16 | X | | X
Add16 | X | | X
Alu | X | | X
FullAdder | | |
HalfAdder | | |
DMux8Way | | |
Mux4Way16 | | |
Mux8Way16 | | |
Or16 | | |
Or8Way | | |
## Sequental
Module | Behavior | Structure | Test coverage
------ | :------: | :-------: | :-----------:
Bit | X | | X
Register | | X | X
RAM8 |
RAM64 |
RAM512 |
RAM4K |
# Prerequisites
* gsed (in script/add.sh)
# Scripts
* scripts/new.sh