https://github.com/pconst/quartus_design_space_explorer_template

Iterative compilation and reporting scripts for Intel / Altera Quartus
https://github.com/pconst/quartus_design_space_explorer_template

Last synced: 4 months ago
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Iterative compilation and reporting scripts for Intel / Altera Quartus

• Host: GitHub
• URL: https://github.com/pconst/quartus_design_space_explorer_template
• Owner: pConst
• Created: 2022-12-07T11:32:43.000Z (over 3 years ago)
• Default Branch: master
• Last Pushed: 2022-12-07T11:34:50.000Z (over 3 years ago)
• Last Synced: 2025-02-28T20:46:16.866Z (over 1 year ago)
• Language: Makefile
• Size: 35.2 KB
• Stars: 5
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          

quartus_design_space_explorer_template

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published as part of https://github.com/pConst/basic_verilog

Konstantin Pavlov, pavlovconst@gmail.com

This project shows how to make iterative compilation for Intel / Altera Quartus FPGA

The idea is similar to the dse.exe utility, that is being shipped with Altera /

Intel Quartus suite

We create a bunch of generated Quartus project copies which differ only one variable

All projects get compiled in parallel collecting FMAX data

This particular test shows FMAX advantage of using 'fast_counter.sv' module

Launch compilation using "make -j". And be careful with large j's there ;)