https://github.com/penberg/riscv-rs

Yet another RISC-V emulator written in Rust.
https://github.com/penberg/riscv-rs

riscv riscv-emulator rust

Last synced: about 1 month ago
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Yet another RISC-V emulator written in Rust.

• Host: GitHub
• URL: https://github.com/penberg/riscv-rs
• Owner: penberg
• Created: 2020-01-06T12:30:44.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2020-01-06T20:46:25.000Z (about 5 years ago)
• Last Synced: 2024-10-13T15:41:29.545Z (3 months ago)
• Topics: riscv, riscv-emulator, rust
• Language: Rust
• Homepage:
• Size: 6.84 KB
• Stars: 0
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# riscv-rs

This is a RISC-V emulator written in Rust.

The goal of this project is to provide a platform for experimenting with extensions to the RISC-V instruction set.

## Roadmap

* [x] ELF support with `mmap()`

* [ ] RV32I instruction set support (_in progress_)

## Getting Started

You can run RISC-V ELF executables with `riscv-rs` as follows:

```

cargo run 

```

For example, download the RISC-V compliance tests and build them:

```

git clone https://github.com/riscv/riscv-compliance

cd riscv-compliance

$ RISCV_PREFIX=riscv64-linux-gnu- make

```

You can then run a test cases as follows:

```

$ cargo run riscv-compliance/work/rv32i/I-ADD-01.elf

```

## License

Licensed under either of

 * Apache License, Version 2.0, ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)

 * MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)

at your option.