https://github.com/penberg/yetanothercore

Yet another RISC-V CPU core
https://github.com/penberg/yetanothercore

riscv systemverilog

Last synced: 4 days ago
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Yet another RISC-V CPU core

• Host: GitHub
• URL: https://github.com/penberg/yetanothercore
• Owner: penberg
• License: mit
• Created: 2019-08-22T12:43:06.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2020-08-16T07:12:20.000Z (over 4 years ago)
• Last Synced: 2024-10-31T03:50:18.428Z (about 2 months ago)
• Topics: riscv, systemverilog
• Language: C
• Homepage:
• Size: 27.3 KB
• Stars: 2
• Watchers: 4
• Forks: 0
• Open Issues: 3
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Yet another CPU core

This is a single-cycle RISC-V core written in SystemVerilog for educational purposes.

## Building from sources

To build everything, type:

```

make

```

## Softwate emulator and simulator

### Building images 

The software emulator and simulator expect animage to be a flat binary. You can generate one with:

```

riscv64-linux-gnu-as tests/alu.S -o tests/alu.o \

  && riscv64-linux-gnu-objcopy -O binary tests/alu.o tests/alu.bin

```

### Running images

To run the generated image with *emulator*, type:

```

./build/rvemu/rvemu tests/alu.bin

```

To run the generated image with *simulator*, type:

```

./build/rvsim/rvsim tests/alu.bin

```

## Other RISC-V cores

https://github.com/tilk/riscv-simple-sv