https://github.com/perehinik/sdram_controller

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice
https://github.com/perehinik/sdram_controller

fpga lattice sdram verilog xilinx

Last synced: 6 days ago
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Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

• Host: GitHub
• URL: https://github.com/perehinik/sdram_controller
• Owner: perehinik
• Created: 2019-05-04T18:58:18.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2021-01-03T12:16:25.000Z (almost 4 years ago)
• Last Synced: 2023-08-03T21:46:37.792Z (over 1 year ago)
• Topics: fpga, lattice, sdram, verilog, xilinx
• Language: VHDL
• Homepage:
• Size: 4.25 MB
• Stars: 11
• Watchers: 3
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# SDRAM_Controller

SDR SDRAM controller for FPGA  Xilinx and Lattice   

Language: Verilog  

Project tested with board Alinx AX309 based on Spartan 6 and custom board based on Lattice MachXO2  

FSM:

![Image](images/FSM.JPG)

Initialization timing diagram:

![Image](images/INIT.JPG)

Write timing diagram:

![Image](images/WRITE.JPG)

Read timing diagram:

![Image](images/READ.JPG)