https://github.com/phillbush/tbgen

Testbench generator in AWK for Verilog modules
https://github.com/phillbush/tbgen

awk testbench testbench-generator testbench-generator-verilog verilog

Last synced: about 2 months ago
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Testbench generator in AWK for Verilog modules

• Host: GitHub
• URL: https://github.com/phillbush/tbgen
• Owner: phillbush
• Created: 2020-08-28T01:44:14.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2021-08-19T19:40:15.000Z (over 3 years ago)
• Last Synced: 2023-03-10T03:57:01.321Z (almost 2 years ago)
• Topics: awk, testbench, testbench-generator, testbench-generator-verilog, verilog
• Language: Shell
• Homepage:
• Size: 23.4 KB
• Stars: 2
• Watchers: 2
• Forks: 1
• Open Issues: 0

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