https://github.com/platform-system-interface/thead_cpuinfo
Decode CPU information for T-Head RISC-V cores
https://github.com/platform-system-interface/thead_cpuinfo
Last synced: about 1 year ago
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Decode CPU information for T-Head RISC-V cores
- Host: GitHub
- URL: https://github.com/platform-system-interface/thead_cpuinfo
- Owner: platform-system-interface
- License: gpl-2.0
- Created: 2024-05-05T19:41:59.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2024-05-05T19:47:44.000Z (almost 2 years ago)
- Last Synced: 2025-01-12T21:07:28.486Z (over 1 year ago)
- Language: Rust
- Size: 10.7 KB
- Stars: 2
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# T-Head cpuinfo
This is a simple CPU information decoder for T-Head cores.
Detailed information is not available regarding model etc. (`CPUINFO0`).
Per the [C906 manual](https://github.com/T-head-Semi/openc906/tree/main/doc):
> The machine mode processor model register (MCPUID) stores the processor
> model information. Its reset value is determined by the product itself and
> complies with the Pingtouge product definition specifications to facilitate
> software identification. By continuously reading the MCPUID register, up to
> 7 different return values can be obtained to represent C906 product
> information, as shown in Figure ??.
(translated by Google)
To read out the register, RISC-V CSR `0xfc0`:
```rs
/// T-Head CPU model register
fn print_cpuid() {
let mut id: u32;
for i in 0..7 {
unsafe { asm!("csrr {}, 0xfc0", out(reg) id) };
println!("MCPUID {i}: {id:08x}");
}
}
```